(1) Field of the Invention
The present invention relates to the fabrication of a dynamic random access memory (DRAMs) device, and more particularly, a fabrication technique for making a ring-type stacked storage capacitor used for charge storage.
(2) Description of the Prior Art
Very large scale integration (VLSI) technologies have greatly increased the circuit density on the chip, and have significantly improved the circuit performance and reduced the cost of todays electronic products. One type of VLSI chip, the dynamic random access memory (DRAMs), is used extensively in the electronic industry and particularly in the computer industry for electrical data storage. These DRAM chips consist of a large array of individual cells, each cell storing a unit of data (one bit) on a capacitor as charge. A single cell is composed of one charge passing transistor, usually a field effect transistor (FET), and a single storage capacitor. In the next 5 to 10 years the number of these cells, on a chip, expected to reach 256 megabits per chip. To achieve these advances in data storage and maintain a reasonable chip size, the individual memory cells, on the chip, must be significantly reduced in size.
As these individual memory cells decrease in size, so must the MOSFET charge passing transistor and the storage capacitor. However, the reduction in the storage capacitor size makes it difficult to store sufficient charge on the capacitor to maintain an acceptable signal-to noise level. Also, these smaller storage capacitors require shorter refresh cycle times to retain the necessary charge level.
These storage capacitor are either formed in the substrate as trench capacitors or as a stacked capacitor on the substrate, usually over the cell area containing the field effect transistor. The stacked capacitor has received much interest in recent years because of the variety of ways that the capacitor can be extended upward over the cell area, increasing its capacitance without requiring additional area on the substrate.
However, these vertical extending capacitors usually require additional processing steps that complicate further the process and increases the cost. For example, P. Fazan in U.S. Pat. No. 5,084,405 teaches a method of depositing a polysilicon layer over an insulating template and then etching back to form a polysilicon sidewall extending upward on the capacitor bottom electrode. Another approach is described by H. H. Tseng in U.S. Pat. No. 5,192,702 in which a self-aligning mask is formed from sidewall spacers, thermal oxidation and the likes are used to etch vertical sidewall in a polysilicon capacitor electrode. Alternatively, non self-aligned vertical walls can also be formed by conventional photolithographic techniques and plasma etching using additional special designed masks.
Although current fabrication methods, of varying complexity, provide a means for fabricating stacked capacitors with increased capacitance, there is still a strong need for processes that minimizes the process complexity while providing good yields at low cost.